1. Field of the Invention
The present invention relates to the design and production of integrated circuits and to the packaging of such circuits, more specifically the invention relates to a ground plane for a semiconductor chip for mounting on a supporting member in a chip package.
2. Description of the Prior Art
In all analog circuit designs it is desirable to have a ground that is as close to 0 volts AC as possible. Normally circuit design assumes that ground nodes do not carry any AC-voltage. If a ground node, contrary to this assumption, does carry an AC-voltage, this may lead to unpredictable behavior, e.g. increased noise, distortion or even instability. The root cause of this is that all conductors have a non-zero impedance. This means that when a ground node has to source or sink a current there will be a voltage drop between the ground node and the actual ground point. This effect is much more pronounced in RF-circuits because the inductive nature of the impedance.
In integrated circuits the ground point of the die (semiconductor chip) is connected to the exterior via a bonding wire connected between the die and the interposer (or leadframe). The impedance of the bonding wire is important at RF-frequencies, and this makes it difficult to realize a proper ground node on the die. If the die is made bigger in order to make the bonding wire shorter, this only moves the problem from the bonding wire to the die because the conductor on the die has to be longer.
Several solutions have been proposed to solve this problem. One is to make the C-package very small and the bonding wires short. This solution has several drawbacks. It is only viable for small scale integration circuits. In large scale integration circuits the die is larger and the ground conductors on the die are correspondingly longer. Moreover for small scale integrated circuits making the bonding wires short only reduces the problem, but does not solve it.
Another solution is to have multiple conductors in parallel. This is often used in RF-PA-stages, but is not really practical for large scale integrated circuits as the multiple connections take up a lot of space
According to a first aspect of the invention, an AC-ground plane is provided for a semiconductor chip for mounting on a supporting member in a chip package, wherein the ground plane comprises at least one first capacitor plate provided within the chip, and at least one second capacitor plate provided on the supporting member, the first and second capacitor plate being separated by a dielectric layer and capacitively coupled to each other via this layer, and the ground plane comprising at least one first conducting member, the first conducting member being at least one electrically conducting via extending through the supporting member and electrically coupled in series with the second capacitor plate.
According to a second aspect of the invention, an AC-ground plane is provided for a semiconductor chip for mounting on a supporting member in a chip package, comprising a capacitor and an inductor having a resonant frequency which approximately equals the working frequency of the integrated circuit.
A third aspect of the invention is a method for providing a tuned RF-ground plane for a semiconductor chip mounted on a supporting member in a chip package. The method includes steps of providing a metal covered area on the surface of the supporting member, and providing a number of vias electrically connected to the metal covered area and extending therefrom through the supporting member to the opposite side thereof, connecting in parallel at least two of the number of vias.
In general terms according to the present invention the problem is solved by placing a metal-covered area on the interposer under the die. Vias on the interposer connect the area to the underside of the interposer. The die is glued to the area with electrically conducting glue. A capacitor is thus formed, the capacitor being formed by the die substrate, the oxide layer on the underside of the die, and the conductive plate on the interposer. By making all other associated impedances as small as possible, e.g. by connecting the metal-plate on the top side of the interposer to the bottom side by using multiple vias in parallel, the resulting impedance can be made very low, less than 20 Ohms, even at high frequencies. If the integrated circuit has a well defined working frequency, the RF-ground plane can be tuned to that frequency by choosing the dimensions of the associated conductors, and thus the inductance of the conductors, so that the resonant frequency of the inductance and capacitor coincides with the working frequency. The impedance at said working frequency can be made extremely low, close to 2 Ohms.
According to a third aspect of the invention, there is provided a semiconductor chip package comprising a semiconductor chip and a supporting member, the supporting member comprising at least one metal covered area and at least one electrically conductive via extending from the metal covered area through the supporting member. The semiconductor chip package is attached to the supporting member by means of conductive glue which is in electrical contact with the metal covered area.